On 25/10/2023 10:41, Konrad Dybcio wrote:
On 10/25/23 09:32, Neil Armstrong wrote:
Add Global Clock Controller (GCC) support for SM8650 platform.
Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
Just a couple remarks
1. looks like there's no usage of shared ops (corresponding
to enable_safe_parent or something along these lines
downstream)
Indeed, it was missing, I'll give a test before posting a v2.
2. none of the GDSCs have interesting flags.. I have this
little cheat sheet that you may find handy:
qcom,retain-regs -> RETAIN_FF_ENABLE
qcom,support-hw-trigger + set_mode in driver -> HW_CONTROL
qcom,no-status-check-on-disable -> VOTABLE
qcom,reset-aon-logic -> AON_RESET
domain-addr = clamp_io_ctrl
Thx, I updated the GDSCs.
3. gcc_cpuss_ubwcp_clk_src uses the XO_A clock as parent, but
it's not there in the ftbl.. Could you confirm whether this
clock should even be accessed from HLOS?
Downstream this clock is only used by gem_noc, since we don't use such
clock upstream I think it's safer to remove it until we have the usage.
[...]
+static int gcc_sm8650_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ int ret;
+
+ regmap = qcom_cc_map(pdev, &gcc_sm8650_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
+ ARRAY_SIZE(gcc_dfs_clocks));
+ if (ret)
+ return ret;
+
+ /*
+ * Keep the critical clock always-On
+ * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
+ * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
+ * gcc_video_xo_clk
+ */
Could you make these comments inline, i.e.
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */
?
Done
Konrad
Thanks,
Neil
