On Thu, 14 Sep 2023 12:29:50 +0530, Kathiravan Thirumoorthy wrote:
> Currently mailbox controller takes the XO and APSS PLL as the input. It
> can take the GPLL0 also as an input. This patch series adds the same and
> fixes the issue caused by this.
>
> Once the cpufreq driver is up, it tries to bump up the cpu frequency
> above 800MHz, while doing so system is going to unusable state. Reason
> being, with the GPLL0 included as clock source, clock framework tries to
> achieve the required rate with the possible parent and since GPLL0
> carries the CLK_SET_RATE_PARENT flag, clock rate of the GPLL0 is getting
> changed, causing the issue.
>
> [...]
Applied, thanks!
[01/11] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
commit: e641a070137dd959932c7c222e000d9d941167a2
[02/11] clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
commit: 99cd4935cb972d0aafb16838bb2aeadbcaf196ce
[03/11] clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
commit: 01a5e4c6731ab6b4b74822661d296f8893fc1230
[04/11] clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
commit: 99a8f8764b70158a712992640a6be46a8fd79d15
[05/11] clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
commit: 5635ef0bd1052420bc659a00be6fd0c60cec5cb9
[07/11] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
commit: e0e6373d653b7707bf042ecf1538884597c5d0da
[08/11] arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox
commit: 80ebe63329909531afc87335f1d95c7bf8414438
[09/11] arm64: dts: qcom: ipq6018: include the GPLL0 as clock provider for mailbox
commit: 0133c7af3aa0420778d106cb90db708cfa45f2c6
[10/11] arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox
commit: 77c726a4f3b124903db5ced7d597976d5b80dcfb
[11/11] arm64: dts: qcom: ipq5332: include the GPLL0 as clock provider for mailbox
commit: da528016952bf93ca810c43fafe518c699db7fa0
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
