On Tue, Oct 17, 2023 at 09:51:29PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 07:24:31AM -0700, Bjorn Andersson wrote:
> > On Tue, Oct 17, 2023 at 11:47:55AM +0530, Manivannan Sadhasivam wrote:
> > > From: Manivannan Sadhasivam <mani@xxxxxxxxxx>
> >
> > Your S-o-b should match this.
> >
>
> I gave b4 a shot for sending the patches and missed this. Will fix it in next
> version.
>
> > >
> > > Qcom EP platforms require enabling/disabling the DBI CS2 access while
> > > programming some read only and shadow registers through DBI. So let's
> > > implement the dbi_cs2_access() callback that will be called by the DWC core
> > > while programming such registers like BAR mask register.
> > >
> > > Without DBI CS2 access, writes to those registers will not be reflected.
> > >
> > > Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver")
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> > > ---
> > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 14 ++++++++++++++
> > > 1 file changed, 14 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > > index 32c8d9e37876..4653cbf7f9ed 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > > @@ -124,6 +124,7 @@
> > >
> > > /* ELBI registers */
> > > #define ELBI_SYS_STTS 0x08
> > > +#define ELBI_CS2_ENABLE 0xa4
> > >
> > > /* DBI registers */
> > > #define DBI_CON_STATUS 0x44
> > > @@ -262,6 +263,18 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
> > > disable_irq(pcie_ep->perst_irq);
> > > }
> > >
> > > +static void qcom_pcie_dbi_cs2_access(struct dw_pcie *pci, bool enable)
> > > +{
> > > + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
> > > +
> > > + writel_relaxed(enable, pcie_ep->elbi + ELBI_CS2_ENABLE);
> >
> > Don't you want to maintain the ordering of whatever write came before
> > this?
> >
>
> Since this in a dedicated function, I did not care about the ordering w.r.t
> previous writes. Even if it gets inlined, the order should not matter since it
> only enables/disables the CS2 access for the forthcoming writes.
>
The wmb() - in a non-relaxed writel - would ensure that no earlier
writes are reordered and end up in your expected set of "forthcoming
writes".
Not sure that the code is wrong, I just want you to be certain that this
isn't a problem.
Thanks,
Bjorn
