On Mon, 16 Oct 2023 at 20:54, Bjorn Andersson <andersson@xxxxxxxxxx> wrote:
>
> On Wed, Oct 04, 2023 at 09:12:30PM +0200, Robert Marko wrote:
> > Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018.
> >
> > Signed-off-by: Robert Marko <robimarko@xxxxxxxxx>
>
> I padded the spi node to 8 digits, and applied the patch.
Thank you for this, it was in my TODO but that is quite long.
Regards,
Robert
>
> Thanks,
> Bjorn
>
> > ---
> > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > index 38ffdc3cbdcd..484034e65f4f 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > @@ -146,6 +146,16 @@ sdhc_1: mmc@7804000 {
> > status = "disabled";
> > };
> >
> > + blsp_dma: dma-controller@7884000 {
> > + compatible = "qcom,bam-v1.7.0";
> > + reg = <0x07884000 0x1d000>;
> > + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&gcc GCC_BLSP1_AHB_CLK>;
> > + clock-names = "bam_clk";
> > + #dma-cells = <1>;
> > + qcom,ee = <0>;
> > + };
> > +
> > blsp1_uart1: serial@78af000 {
> > compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> > reg = <0x078af000 0x200>;
> > @@ -156,6 +166,20 @@ blsp1_uart1: serial@78af000 {
> > status = "disabled";
> > };
> >
> > + blsp1_spi1: spi@78b5000 {
> > + compatible = "qcom,spi-qup-v2.2.1";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x78b5000 0x600>;
> > + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
> > + <&gcc GCC_BLSP1_AHB_CLK>;
> > + clock-names = "core", "iface";
> > + dmas = <&blsp_dma 4>, <&blsp_dma 5>;
> > + dma-names = "tx", "rx";
> > + status = "disabled";
> > + };
> > +
> > intc: interrupt-controller@b000000 {
> > compatible = "qcom,msm-qgic2";
> > reg = <0x0b000000 0x1000>, /* GICD */
> > --
> > 2.41.0
> >
