On 10/7/23 17:48, Krishna Kurapati wrote:
From: Andrew Halaney <ahalaney@xxxxxxxxxx> There is now support for the multiport USB controller this uses so enable it. The board only has a single port hooked up (despite it being wired up to the multiport IP on the SoC). There's also a USB 2.0 mux hooked up, which by default on boot is selected to mux properly. Grab the gpio controlling that and ensure it stays in the right position so USB 2.0 continues to be routed from the external port to the SoC. Co-developed-by: Andrew Halaney <ahalaney@xxxxxxxxxx> Signed-off-by: Andrew Halaney <ahalaney@xxxxxxxxxx> [Krishna: Rebased on top of usb-next] Co-developed-by: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx> Signed-off-by: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx> --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index b04f72ec097c..6904a4c201ff 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -503,6 +503,18 @@ &usb_2_qmpphy0 { status = "okay"; };+&usb_2 {+ pinctrl-0 = <&usb2_en_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb_2_dwc3 {
These additions are not quite sorted alphabetically, it seems
+ phy-names = "usb2-port0", "usb3-port0"; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
property property-names With that: Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> Konrad
