Starting with the SM8550 platform, the SSPP & WB Clock Controls are no more in the MDP TOP registers, but in the SSPP & WB register space. Add the corresponding SSPP & WB ops and use them before/after calling the QoS and OT limit setup functions. Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> --- Changes in v2: - moved all force_clk_ctrl code out of vbif - use major ver test to add force_clk_ctrl op - do not add clk_ctrl reg into sspp/wb cap struct - add WB2 on sm8550 - Link to v1: https://lore.kernel.org/r/20231009-topic-sm8550-graphics-sspp-split-clk-v1-0-806c0dee4e43@xxxxxxxxxx --- Neil Armstrong (5): drm/msm/dpu: create a dpu_hw_clk_force_ctrl() helper drm/msm/dpu: add setup_clk_force_ctrl() op to sspp & wb drm/msm/dpu: move setup_force_clk_ctrl handling into plane and wb drm/msm/dpu: sm8550: remove unused VIG and DMA clock controls entries drm/msm/dpu: enable writeback on SM8550 .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 36 +++++++++---------- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 37 +++++++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 21 +++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 12 ++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 23 +----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 20 +++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 7 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 42 +++++++++++++++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 4 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 30 +++------------- drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h | 4 --- 13 files changed, 173 insertions(+), 88 deletions(-) --- base-commit: 9119cf579b4432b36be9d33a92f4331922067d92 change-id: 20231009-topic-sm8550-graphics-sspp-split-clk-43c32e37b6aa Best regards, -- Neil Armstrong <neil.armstrong@xxxxxxxxxx>
