On 10/11/23 11:00, Imran Shaik wrote:
From: Taniya Das <quic_tdas@xxxxxxxxxxx>
Clock CBCRs with memories need an update for memory before enable/disable
of the clock, which helps retain the respective block's register contents.
Add support for the mem ops to handle this sequence.
Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
Signed-off-by: Imran Shaik <quic_imrashai@xxxxxxxxxxx>
---
drivers/clk/qcom/clk-branch.c | 37 +++++++++++++++++++++++++++++++++++
drivers/clk/qcom/clk-branch.h | 21 ++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index fc4735f74f0f..9ac8d04b425a 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/kernel.h>
@@ -134,6 +135,42 @@ static void clk_branch2_disable(struct clk_hw *hw)
clk_branch_toggle(hw, false, clk_branch2_check_halt);
}
+static int clk_branch2_mem_enable(struct clk_hw *hw)
+{
+ struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
+ const char *name = clk_hw_get_name(&mem_br->branch.clkr.hw);
+ u32 val;
+ int timeout = 200, ret;
Reverse-Christmas-tree, please
You can drop the timeout variable and pass the int literal.
+
+ regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg,
+ mem_br->mem_enable_ack_bit, mem_br->mem_enable_ack_bit);
This is a mask, not a bit.
+
+ ret = regmap_read_poll_timeout(mem_br->branch.clkr.regmap, mem_br->mem_ack_reg,
+ val, val & mem_br->mem_enable_ack_bit, 0, timeout);
[...]
+/**
+ * struct clk_mem_branch - gating clock which are associated with memories
+ *
+ * @mem_enable_reg: branch clock memory gating register
+ * @mem_ack_reg: branch clock memory ack register
+ * @mem_enable_ack_bit: ANDed with @mem_ack_reg to check memory enablement
@dog: woofs
Describe what it is instead.
Konrad
