On Wed, Sep 20, 2023 at 07:25:10PM +0530, Mrinmay Sarkar wrote:
> Add support for dual lane end point mode PHY found on sa8755p platform.
>
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@xxxxxxxxxxx>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 41 ++++++++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 2 ++
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h | 1 +
> 3 files changed, 44 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index a63ca74..351047c 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -2147,6 +2147,38 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[]
> QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> };
>
> +static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CMN_MODE, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
> +};
> +
> +static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_ep_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_INSIG_MX_CTRL7, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_INSIG_SW_CTRL7, 0x00),
> +};
> +
> struct qmp_pcie_offsets {
> u16 serdes;
> u16 pcs;
> @@ -3043,6 +3075,15 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
> .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
> },
>
> + .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
> + .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
> + .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
> + .pcs_misc = sa8775p_qmp_gen4_pcie_ep_pcs_misc_tbl,
> + .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_ep_pcs_misc_tbl),
> + .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl,
> + .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl),
> + },
> +
> .reset_list = sdm845_pciephy_reset_l,
> .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> .vreg_list = qmp_phy_vreg_l,
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> index 36cc80b..2b33dc7 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> @@ -30,5 +30,7 @@
> #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
> #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
> #define QPHY_V5_PCS_EQ_CONFIG5 0x1ec
> +#define QPHY_V5_PCS_INSIG_MX_CTRL7 0x07c
> +#define QPHY_V5_PCS_INSIG_SW_CTRL7 0x060
Sort the defines please, here and below.
- Mani
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
> index c8afdf7..ad587c8 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
> @@ -120,5 +120,6 @@
> #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
> #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
> #define QSERDES_V5_COM_RESERVED_1 0x1c0
> +#define QSERDES_V5_COM_PLL_CMN_MODE 0x1a0
>
> #endif
> --
> 2.7.4
>
--
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