On 7.09.2023 07:21, Varadarajan Narayanan wrote: > Stromer plus APSS PLL does not support dynamic frequency scaling. > To switch between frequencies, we have to shut down the PLL, > configure the L and ALPHA values and turn on again. So introduce the > separate set of ops for Stromer Plus PLL. > > Signed-off-by: Kathiravan T <quic_kathirav@xxxxxxxxxxx> > Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx> > --- [...] > + > + /* Wait five micro seconds or more */ > + udelay(5); > + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, > + PLL_RESET_N); > + > + /* The lock time should be less than 50 micro seconds worst case */ > + udelay(50); https://www.kernel.org/doc/Documentation/timers/timers-howto.txt > + > + ret = wait_for_pll_enable_lock(pll); > + if (ret) { > + pr_err("alpha pll running in 800 MHz with source GPLL0\n"); > + return ret; > + } Would that not be SoC-specific information? Konrad
