On 07/09/2023 07:21, Varadarajan Narayanan wrote:
> IPQ95xx SoCs have different OPPs available for the CPU based on
> SoC variant. This can be determined from an eFuse register
> present in the silicon.
>
> Add support to read the eFuse and populate the OPPs based on it.
>
...
> };
> @@ -223,6 +254,11 @@
> reg = <0x000a4000 0x5a1>;
> #address-cells = <1>;
> #size-cells = <1>;
> +
> + cpu_speed_bin: cpu_speed_bin@15 {
No underscores in node names
Best regards,
Krzysztof
