On 01/09/2023 14:28, Konrad Dybcio wrote:
> On 1.09.2023 11:02, Krzysztof Kozlowski wrote:
>> Existing Qualcomm SoCs have the LPASS pin controller slew rate control
>> in separate register, however this will change with upcoming Qualcomm
>> SoCs. The slew rate will be part of the main register for pin
>> configuration, thus second device IO address space is not needed.
>>
>> Prepare for supporting new SoCs by adding flag customizing the driver
>> behavior for slew rate.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>> ---
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 20 ++++++++++++++------
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 7 +++++++
>> 2 files changed, 21 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> index e2df2193a802..40eb58a3a8cd 100644
>> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> @@ -190,6 +190,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
>> const struct lpi_pingroup *g,
>> unsigned int group, unsigned int slew)
>> {
>> + void __iomem *reg;
> Aaalmost reverse-Christmas-tree!
I can fix it.
>
>> unsigned long sval;
>> int slew_offset;
>>
>> @@ -203,12 +204,17 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
>> if (slew_offset == LPI_NO_SLEW)
>> return 0;
>>
>> + if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)
>> + reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;
>> + else
>> + reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;
> Perhaps lpi_gpio_read/write could be used here?
>
> I guess both ways work though
I was thinking about this, but decided not to in favor of duplicating
"tlmm_base + offset * group ....". It would not make the code easier to
read.
Best regards,
Krzysztof
