On certain targets (eg, MSM8996) we need to set the following
domain attribute for correct operation of the SMMU:
DOMAIN_ATTR_COHERENT_HTW_DISABLE.
Setting that attribute is very important on 8996. Without it, we would
see crazy translation faults.
Note:
There could be support for coherent hardware table walks in
the future
Signed-off-by: Stephane Viau <sviau@xxxxxxxxxxxxxx>
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index bbab6e6..14ac20a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -584,6 +584,8 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
mdelay(16);
if (config->platform.iommu) {
+ int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg);
+
mmu = msm_iommu_new(&pdev->dev, config->platform.iommu);
if (IS_ERR(mmu)) {
ret = PTR_ERR(mmu);
@@ -591,6 +593,19 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
goto fail;
}
+ /*
+ * On certain targets (8996, for example) we need to set the
+ * following domain attribute for correct operation of the SMMU;
+ * Without it, we would see crazy translation faults..
+ */
+ if (rev == 7) {
+ int disable_htw = 1;
+
+ iommu_domain_set_attr(config->platform.iommu,
+ DOMAIN_ATTR_COHERENT_HTW_DISABLE, &disable_htw);
+ DBG("coherent hardware translation table walks is off");
+ }
+
ret = mmu->funcs->attach(mmu, iommu_ports,
ARRAY_SIZE(iommu_ports));
if (ret) {
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
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