On Mon, 21 Aug 2023 at 03:25, Dmitry Baryshkov
<dmitry.baryshkov@xxxxxxxxxx> wrote:
>
> Change the USB QMP PHY to use newer style of QMP PHY bindings (single
> resource region, no per-PHY subnodes).
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 39 +++++++++++----------------
> 1 file changed, 16 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index 30d8730fa4de..46a6ef0e454b 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -979,12 +979,12 @@ pcie_phy: phy@1c06000 {
> status = "disabled";
>
> clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> - <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> <&gcc GCC_PCIE_CLKREF_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> <&gcc GCC_PCIE_0_PIPE_CLK>;
> clock-names = "aux",
> - "cfg_ahb",
> "ref",
> + "cfg_ahb",
> "pipe";
This chunk changes the PCIe PHY and as such doesn't belong to this patch.
>
> clock-output-names = "pcie_0_pipe_clk_src";
> @@ -2138,7 +2138,7 @@ usb3_dwc3: usb@a800000 {
> interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> snps,dis_u2_susphy_quirk;
> snps,dis_enblslpm_quirk;
> - phys = <&qusb2phy>, <&usb1_ssphy>;
> + phys = <&qusb2phy>, <&usb3phy>;
> phy-names = "usb2-phy", "usb3-phy";
> snps,has-lpm-erratum;
> snps,hird-threshold = /bits/ 8 <0x10>;
> @@ -2147,33 +2147,26 @@ usb3_dwc3: usb@a800000 {
>
> usb3phy: phy@c010000 {
> compatible = "qcom,msm8998-qmp-usb3-phy";
> - reg = <0x0c010000 0x18c>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> + reg = <0x0c010000 0x1000>;
>
> clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
> + <&gcc GCC_USB3_CLKREF_CLK>,
> <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> - <&gcc GCC_USB3_CLKREF_CLK>;
> - clock-names = "aux", "cfg_ahb", "ref";
> + <&gcc GCC_USB3_PHY_PIPE_CLK>;
> + clock-names = "aux",
> + "ref",
> + "cfg_ahb",
> + "pipe";
> + clock-output-names = "usb3_phy_pipe_clk_src";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
>
> resets = <&gcc GCC_USB3_PHY_BCR>,
> <&gcc GCC_USB3PHY_PHY_BCR>;
> - reset-names = "phy", "common";
> + reset-names = "phy",
> + "phy_phy";
>
> - usb1_ssphy: phy@c010200 {
> - reg = <0xc010200 0x128>,
> - <0xc010400 0x200>,
> - <0xc010c00 0x20c>,
> - <0xc010600 0x128>,
> - <0xc010800 0x200>;
> - #phy-cells = <0>;
> - #clock-cells = <0>;
> - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
> - clock-names = "pipe0";
> - clock-output-names = "usb3_phy_pipe_clk_src";
> - };
> + status = "disabled";
> };
>
> qusb2phy: phy@c012000 {
> --
> 2.39.2
>
--
With best wishes
Dmitry
