Hi, On 23/08/2023 07:35, Maulik Shah (mkshah) wrote:
Hi Neil, @@ -142,8 +163,17 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)return -EINVAL; } - old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); - pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); + if (pdc_version < PDC_VERSION_3_2) { + old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); + pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); + } else { + u32 val; + + val = pdc_reg_read(IRQ_i_CFG, d->hwirq); + old_pdc_type = val & IRQ_i_CFG_TYPE_MASK; + pdc_reg_write(IRQ_i_CFG, d->hwirq, + pdc_type | (val & IRQ_i_CFG_IRQ_ENABLE)); + }While above is correct, i don't think we need version check in qcom_pdc_gic_set_type() as bits 0-2 are always for the type in old/new version as mentioned in v1. Adding one line after reading old_pdc_type should be good enough.
Yes I understood, but while looking at the IRQ_i_CFG bits, I wanted to keep the original driver behavior intact by setting remaining bits to 0. Adding this single line changes that behavior and keeps bits 3-31 to the default register value, which may have some consequences. If you consider it's an ok change, then I'll reduce it to this single line.
old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); + pdc_type |= (old_pdc_type & ~IRQ_i_CFG_TYPE_MASK);+ if (pdc_version < PDC_VERSION_3_2) { + u32 irq_index, reg_index; + + reg_index = (i + pdc_region[n].pin_base) >> 5; + irq_index = (i + pdc_region[n].pin_base) & 0x1f; + val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index); + val &= ~BIT(irq_index);can use __assign_bit(irq_index, &val, 0); here.+ pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val); + } else { + u32 irq; + + irq = i + pdc_region[n].pin_base; + val = pdc_reg_read(IRQ_i_CFG, irq); + val &= ~IRQ_i_CFG_IRQ_ENABLE;__assign_bit(IRQ_i_CFG_IRQ_ENABLE, &val, 0); here.
Ack I'll update those.
other than this.. Reviewed-by: Maulik Shah <quic_mkshah@xxxxxxxxxxx> Thanks, Maulik
Thanks, Neil
