From: Jie Luo <quic_luoj@xxxxxxxxxxx> qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode named by qca8386, working as PHY mode named by qca8084, clock hardware reigster is accessed by MDIO bus. This patch series add the clock controller of qca8363/qca8084, and add the clock flag CLK_ENABLE_MUTEX_LOCK to avoid spin lock used during the clock operation of qca8k clock controller where the sleep happens when accessing clock control register by MDIO bus. Luo Jie (3): clk: Add the flag CLK_ENABLE_MUTEX_LOCK of enabling clock dt-bindings: clock: add qca8386/qca8084 clock and reset definitions clk: qcom: add clock controller driver for qca8386/qca8084 .../bindings/clock/qcom,nsscc-qca8k.yaml | 59 + drivers/clk/clk.c | 78 +- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/nsscc-qca8k.c | 2205 +++++++++++++++++ include/dt-bindings/clock/qcom,nsscc-qca8k.h | 102 + include/dt-bindings/reset/qcom,nsscc-qca8k.h | 76 + include/linux/clk-provider.h | 4 + 8 files changed, 2519 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml create mode 100644 drivers/clk/qcom/nsscc-qca8k.c create mode 100644 include/dt-bindings/clock/qcom,nsscc-qca8k.h create mode 100644 include/dt-bindings/reset/qcom,nsscc-qca8k.h base-commit: ec89391563792edd11d138a853901bce76d11f44 -- 2.34.1
