On 31.07.2023 12:57, Dmitry Baryshkov wrote:
> Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
> resource region, no per-PHY subnodes).
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 36 ++++++++++------------------
> 1 file changed, 12 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 4353f7265877..670092731c6c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -869,7 +869,7 @@ gcc: clock-controller@100000 {
> reg = <0 0x00100000 0 0x1f0000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> - <0>, <&pcie1_lane>,
> + <0>, <&pcie1_phy>,
> <0>, <0>, <0>,
> <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> @@ -2121,7 +2121,7 @@ pcie1: pci@1c08000 {
>
> clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
> - <&pcie1_lane>,
> + <&pcie1_phy>,
> <&rpmhcc RPMH_CXO_CLK>,
> <&gcc GCC_PCIE_1_AUX_CLK>,
> <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> @@ -2155,7 +2155,7 @@ pcie1: pci@1c08000 {
>
> power-domains = <&gcc GCC_PCIE_1_GDSC>;
>
> - phys = <&pcie1_lane>;
> + phys = <&pcie1_phy>;
> phy-names = "pciephy";
>
> pinctrl-names = "default";
> @@ -2171,15 +2171,18 @@ pcie1: pci@1c08000 {
>
> pcie1_phy: phy@1c0e000 {
> compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
> - reg = <0 0x01c0e000 0 0x1c0>;
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> + reg = <0 0x01c0e000 0 0x1000>;
> clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> <&gcc GCC_PCIE_CLKREF_EN>,
> - <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
> - clock-names = "aux", "cfg_ahb", "ref", "refgen";
> + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_1_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe";
1 per line, pretty please?
Konrad
