On 31.07.2023 12:57, Dmitry Baryshkov wrote:
> Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
> resource region, no per-PHY subnodes).
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 63 +++++++++++----------------
> 1 file changed, 26 insertions(+), 37 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 00ed71936b47..e4447a9d7929 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -211,59 +211,48 @@ qusb_phy_0: phy@79000 {
>
> pcie_qmp0: phy@84000 {
> compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
> - reg = <0x00084000 0x1bc>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> + reg = <0x00084000 0x1000>;
>
> clocks = <&gcc GCC_PCIE0_AUX_CLK>,
> - <&gcc GCC_PCIE0_AHB_CLK>;
> - clock-names = "aux", "cfg_ahb";
> + <&gcc GCC_PCIE0_AHB_CLK>,
> + <&gcc GCC_PCIE0_PIPE_CLK>;
Can you align the clocks entries?
Konrad
