On 28/07/2023 17:10, Krishna Chaitanya Chundru wrote:
>
> On 7/28/2023 5:33 PM, Krzysztof Kozlowski wrote:
>> On 28/07/2023 12:39, Krishna chaitanya chundru wrote:
>>> Add PCIe dtsi node for PCIe0 controller on sc7280 platform.
>>>
>>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>
>>> + pcie0_phy: phy@1c06000 {
>>> + compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
>>> + reg = <0 0x01c06000 0 0x1c0>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges;
>>> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>>> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>>> + <&gcc GCC_PCIE_CLKREF_EN>,
>>> + <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
>>> + clock-names = "aux", "cfg_ahb", "ref", "refgen";
>>> +
>>> + resets = <&gcc GCC_PCIE_0_PHY_BCR>;
>>> + reset-names = "phy";
>>> +
>>> + assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
>>> + assigned-clock-rates = <100000000>;
>>> +
>>> + status = "disabled";
>>> +
>>> + pcie0_lane: phy@1c0e6200 {
>> Isn't this old-style of bindings? Wasn't there a change? On what tree
>> did you base it?
The work was here:
https://lore.kernel.org/all/20230324022514.1800382-5-dmitry.baryshkov@xxxxxxxxxx/
But I don't remember the status.
> Let me rebase and send it again.
This anyway looks like wrong compatible. You used sm8250.
Best regards,
Krzysztof
