Please exuse me for the spam, I missed the triggered WARN_ON because of the dropped patch. Declaring the mask of supported interrupts proved to be error-prone. It is very easy to add a bit with no corresponding backing block or to miss the INTF TE bit. Replace this static configuration with the irq mask calculated from the HW catalog data. Changes since v3: - Rework INTF_TE handling. Stop depending on DPU_INTF_TE and enable the relevant interrupt explicitly. Changes since v2: - Rebased on top of msm-next-lumag to be able to use core_major_ver instead of adding yet another flag. - Dropped the DPU_INTF_TE movement patch, useless after rebasing. Changes since v1: - Enable dpu_caps::has_7xxx_intr for DPU >= 7.0 (Neil) Dmitry Baryshkov (5): drm/msm/dpu: inline __intr_offset drm/msm/dpu: split interrupt address arrays drm/msm/dpu: autodetect supported interrupts drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog drm/msm/dpu: drop compatibility INTR defines .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 -- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 9 -- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 11 -- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 13 --- .../msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 - .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 10 -- .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 6 - .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 5 - .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 6 - .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 5 - .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 5 - .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 13 +-- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 9 +- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 18 +-- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 13 +-- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 13 +-- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 - .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 106 ++++++++++++------ .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 18 ++- 19 files changed, 87 insertions(+), 190 deletions(-) -- 2.39.2
