On 25.07.2023 10:02, Konrad Dybcio wrote:
> On 23.07.2023 18:08, Adam Skladowski wrote:
>> Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL.
>> Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz.
>> For simplicity only add second range as smaller frequencies can be obtained
>> via apcs divider or safe parent this also saves us
>> a hassle of reconfiguring VCO bit and config_val.
>> A72 and CCI cluster only use single frequency range with their
>> outputs/post_dividers/vco_bits being static.
>>
>> Signed-off-by: Adam Skladowski <a39.skl@xxxxxxxxx>
>> ---
> [...]
>
>> +static const struct hfpll_data msm8976_a72 = {
>> + .mode_reg = 0x00,
>> + .l_reg = 0x04,
>> + .m_reg = 0x08,
>> + .n_reg = 0x0c,
>> + .user_reg = 0x10,
>> + .config_reg = 0x14,
>> + .config_val = 0x4e0405d,
>> + .status_reg = 0x1c,
>> + .lock_bit = 16,
>> +
>> + .l_val = 0x3e,
>> + .user_val = 0x100109,
>> + .min_rate = 940800000UL,
>> + .max_rate = 1843200000UL,
> 2016000000?
We are using msm kernel as base not SODP ports.
https://android.googlesource.com/kernel/msm/+/android-lego-6.0.1_r0.2/drivers/clk/qcom/clock-cpu-8976.c
https://android.googlesource.com/kernel/msm.git/+/android-msm-lego-3.10-marshmallow-dr/arch/arm/boot/dts/qcom/msm8976.dtsi#349
> [...]
>> static const struct of_device_id qcom_hfpll_match_table[] = {
>> { .compatible = "qcom,hfpll", &hdata },
>> + { .compatible = "qcom,msm8976-hfpll-a53", &msm8976_a53 },
>> + { .compatible = "qcom,msm8976-hfpll-a72", &msm8976_a72 },
>> + { .compatible = "qcom,msm8976-hfpll-cci", &msm8976_cci },
> .data = is missing
>
> Konrad
Seems like i took "inspiration" from also not great code, albeit it does work somehow when printing inside init, will fix in v3
Thanks Angelo/Konrad
