On Wed, Jul 19, 2023 at 12:50:17PM +0530, Krishna chaitanya chundru wrote: > Add cpu-pcie interconnect path for PCIe EP to sdx55 platform. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > --- > arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi > index df3cd9c..a7c0c26 100644 > --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi > +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi > @@ -422,8 +422,9 @@ > interrupt-names = "global", > "doorbell"; > > - interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; > - interconnect-names = "pcie-mem"; > + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, > + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>; > + interconnect-names = "pcie-mem", "cpu-pcie"; > > resets = <&gcc GCC_PCIE_BCR>; > reset-names = "core"; > -- > 2.7.4 > -- மணிவண்ணன் சதாசிவம்
