On Wed, Jul 12, 2023 at 07:18:12AM +0530, Satya Priya Kakitapalli wrote:
> From: Taniya Das <quic_tdas@xxxxxxxxxxx>
>
> If rcg is in disabled state when clk_rcg2_shared_set_rate is called, the
> new configuration is written to the configuration register but it won't be
> effective in h/w yet because update bit won't be set if rcg is in disabled
> state. Since the new configuration is not yet updated in h/w, dirty bit of
> configuration register will be set in such case. Clear the dirty bit and
> update the rcg to proper new configuration by setting the update bit before
> enabling the rcg.
>
If I understand correctly you're saying that without this patch:
devm_clk_get();
clk_set_rate(rate);
clk_prepare_enable();
would look like it worked (i.e. clk_get_rate() would return rate), but
in reality the clock is running at whatever the "default" rate is.
That sounds like it could use a Fixes: tag if so!
Thanks,
Andrew
