On 17.07.2023 18:56, Stephan Gerhold wrote:
> On Mon, Jul 17, 2023 at 06:50:18PM +0200, Konrad Dybcio wrote:
>> On 17.07.2023 18:28, Stephan Gerhold wrote:
>>> On Mon, Jul 17, 2023 at 05:19:22PM +0200, Konrad Dybcio wrote:
>>>> The GPU_CC block is powered by VDD_CX. Describe that.
>>>>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++
>>>> 1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>>> index 29b5b388cd94..bfaaa1801a4d 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>>> @@ -1430,6 +1430,8 @@ gpucc: clock-controller@5990000 {
>>>> clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
>>>> <&gcc GCC_GPU_GPLL0_CLK_SRC>,
>>>> <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
>>>> + power-domains = <&rpmpd SM6115_VDDCX>;
>>>> + required-opps = <&rpmpd_opp_low_svs>;
>>>
>>> Where is this required-opp coming from? The clocks in gpucc seem to have
>>> different voltage requirements depending on the rates, but we usually
>>> handle that in the OPP tables of the consumer.
>> The only lower levels defined for this SoC are VDD_MIN and VDD_RET,
>> but quite obviously the GPU won't work then
>>
>
> The levels needed for the GPU clocks to run should be in the GPU OPP
> table though, just like e.g. sdhc2_opp_table for the SDCC clocks.
>
> I still don't really understand why this is specified here. :)
The GPU_CC block needs this rail to be at a certain power level for
register access. This describes that requirement.
Konrad
