On 13.07.2023 12:59, Anusha Rao wrote:
> Add a dtsi file to include interfaces that are common
> across RDPs.
>
> Signed-off-by: Anusha Rao <quic_anusha@xxxxxxxxxxx>
> ---
[...]
> data-pins {
> pins = "gpio0", "gpio1", "gpio2",
> - "gpio3", "gpio6", "gpio7",
> - "gpio8", "gpio9";
> + "gpio3", "gpio6", "gpio7",
> + "gpio8", "gpio9";
This (and a similar one in the other file) change looks unrelated
and I think it makes the indentation worse :/
Konrad
> function = "sdc_data";
> drive-strength = <8>;
> bias-pull-up;
> @@ -110,15 +60,4 @@
> bias-pull-down;
> };
> };
> -
> - spi_0_pins: spi-0-state {
> - pins = "gpio11", "gpio12", "gpio13", "gpio14";
> - function = "blsp0_spi";
> - drive-strength = <8>;
> - bias-disable;
> - };
> -};
> -
> -&xo_board_clk {
> - clock-frequency = <24000000>;
> };
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> index 877026ccc6e2..7685176f90ef 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> @@ -8,69 +8,11 @@
>
> /dts-v1/;
>
> -#include "ipq9574.dtsi"
> +#include "ipq9574-rdp-common.dtsi"
>
> / {
> model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
> compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
> -
> - aliases {
> - serial0 = &blsp1_uart2;
> - };
> -
> - chosen {
> - stdout-path = "serial0:115200n8";
> - };
> -
> - regulator_fixed_3p3: s3300 {
> - compatible = "regulator-fixed";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-boot-on;
> - regulator-always-on;
> - regulator-name = "fixed_3p3";
> - };
> -
> - regulator_fixed_0p925: s0925 {
> - compatible = "regulator-fixed";
> - regulator-min-microvolt = <925000>;
> - regulator-max-microvolt = <925000>;
> - regulator-boot-on;
> - regulator-always-on;
> - regulator-name = "fixed_0p925";
> - };
> -};
> -
> -&blsp1_uart2 {
> - pinctrl-0 = <&uart2_pins>;
> - pinctrl-names = "default";
> - status = "okay";
> -};
> -
> -&rpm_requests {
> - regulators {
> - compatible = "qcom,rpm-mp5496-regulators";
> -
> - ipq9574_s1: s1 {
> - /*
> - * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
> - * During regulator registration, kernel not knowing the initial voltage,
> - * considers it as zero and brings up the regulators with minimum supported voltage.
> - * Update the regulator-min-microvolt with SVS voltage of 725mV so that
> - * the regulators are brought up with 725mV which is sufficient for all the
> - * corner parts to operate at 800MHz
> - */
> - regulator-min-microvolt = <725000>;
> - regulator-max-microvolt = <1075000>;
> - };
> -
> - mp5496_l2: l2 {
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> - };
> };
>
> &sdhc_1 {
> @@ -85,10 +27,6 @@
> status = "okay";
> };
>
> -&sleep_clk {
> - clock-frequency = <32000>;
> -};
> -
> &tlmm {
> sdc_default_state: sdc-default-state {
> clk-pins {
> @@ -107,8 +45,8 @@
>
> data-pins {
> pins = "gpio0", "gpio1", "gpio2",
> - "gpio3", "gpio6", "gpio7",
> - "gpio8", "gpio9";
> + "gpio3", "gpio6", "gpio7",
> + "gpio8", "gpio9";
> function = "sdc_data";
> drive-strength = <8>;
> bias-pull-up;
> @@ -122,30 +60,3 @@
> };
> };
> };
> -
> -&usb_0_dwc3 {
> - dr_mode = "host";
> -};
> -
> -&usb_0_qmpphy {
> - vdda-pll-supply = <&mp5496_l2>;
> - vdda-phy-supply = <®ulator_fixed_0p925>;
> -
> - status = "okay";
> -};
> -
> -&usb_0_qusbphy {
> - vdd-supply = <®ulator_fixed_0p925>;
> - vdda-pll-supply = <&mp5496_l2>;
> - vdda-phy-dpdm-supply = <®ulator_fixed_3p3>;
> -
> - status = "okay";
> -};
> -
> -&usb3 {
> - status = "okay";
> -};
> -
> -&xo_board_clk {
> - clock-frequency = <24000000>;
> -};
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
> index c8fa54e1a62c..d36d1078763e 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
> @@ -8,73 +8,10 @@
>
> /dts-v1/;
>
> -#include "ipq9574.dtsi"
> +#include "ipq9574-rdp-common.dtsi"
>
> / {
> model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6";
> compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";
>
> - aliases {
> - serial0 = &blsp1_uart2;
> - };
> -
> - chosen {
> - stdout-path = "serial0:115200n8";
> - };
> -};
> -
> -&blsp1_spi0 {
> - pinctrl-0 = <&spi_0_pins>;
> - pinctrl-names = "default";
> - status = "okay";
> -
> - flash@0 {
> - compatible = "micron,n25q128a11", "jedec,spi-nor";
> - reg = <0>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - spi-max-frequency = <50000000>;
> - };
> -};
> -
> -&blsp1_uart2 {
> - pinctrl-0 = <&uart2_pins>;
> - pinctrl-names = "default";
> - status = "okay";
> -};
> -
> -&rpm_requests {
> - regulators {
> - compatible = "qcom,rpm-mp5496-regulators";
> -
> - ipq9574_s1: s1 {
> - /*
> - * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
> - * During regulator registration, kernel not knowing the initial voltage,
> - * considers it as zero and brings up the regulators with minimum supported voltage.
> - * Update the regulator-min-microvolt with SVS voltage of 725mV so that
> - * the regulators are brought up with 725mV which is sufficient for all the
> - * corner parts to operate at 800MHz
> - */
> - regulator-min-microvolt = <725000>;
> - regulator-max-microvolt = <1075000>;
> - };
> - };
> -};
> -
> -&sleep_clk {
> - clock-frequency = <32000>;
> -};
> -
> -&tlmm {
> - spi_0_pins: spi-0-state {
> - pins = "gpio11", "gpio12", "gpio13", "gpio14";
> - function = "blsp0_spi";
> - drive-strength = <8>;
> - bias-disable;
> - };
> -};
> -
> -&xo_board_clk {
> - clock-frequency = <24000000>;
> };
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
> index f01de6628c3b..c30c9fbedf26 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
> @@ -8,73 +8,10 @@
>
> /dts-v1/;
>
> -#include "ipq9574.dtsi"
> +#include "ipq9574-rdp-common.dtsi"
>
> / {
> model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8";
> compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
>
> - aliases {
> - serial0 = &blsp1_uart2;
> - };
> -
> - chosen {
> - stdout-path = "serial0:115200n8";
> - };
> -};
> -
> -&blsp1_spi0 {
> - pinctrl-0 = <&spi_0_pins>;
> - pinctrl-names = "default";
> - status = "okay";
> -
> - flash@0 {
> - compatible = "micron,n25q128a11", "jedec,spi-nor";
> - reg = <0>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - spi-max-frequency = <50000000>;
> - };
> -};
> -
> -&blsp1_uart2 {
> - pinctrl-0 = <&uart2_pins>;
> - pinctrl-names = "default";
> - status = "okay";
> -};
> -
> -&rpm_requests {
> - regulators {
> - compatible = "qcom,rpm-mp5496-regulators";
> -
> - ipq9574_s1: s1 {
> - /*
> - * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
> - * During regulator registration, kernel not knowing the initial voltage,
> - * considers it as zero and brings up the regulators with minimum supported voltage.
> - * Update the regulator-min-microvolt with SVS voltage of 725mV so that
> - * the regulators are brought up with 725mV which is sufficient for all the
> - * corner parts to operate at 800MHz
> - */
> - regulator-min-microvolt = <725000>;
> - regulator-max-microvolt = <1075000>;
> - };
> - };
> -};
> -
> -&sleep_clk {
> - clock-frequency = <32000>;
> -};
> -
> -&tlmm {
> - spi_0_pins: spi-0-state {
> - pins = "gpio11", "gpio12", "gpio13", "gpio14";
> - function = "blsp0_spi";
> - drive-strength = <8>;
> - bias-disable;
> - };
> -};
> -
> -&xo_board_clk {
> - clock-frequency = <24000000>;
> };
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
> index 6efae3426cb8..0dc382f5d5ec 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
> @@ -8,73 +8,9 @@
>
> /dts-v1/;
>
> -#include "ipq9574.dtsi"
> +#include "ipq9574-rdp-common.dtsi"
>
> / {
> model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
> compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
> -
> - aliases {
> - serial0 = &blsp1_uart2;
> - };
> -
> - chosen {
> - stdout-path = "serial0:115200n8";
> - };
> -};
> -
> -&blsp1_spi0 {
> - pinctrl-0 = <&spi_0_pins>;
> - pinctrl-names = "default";
> - status = "okay";
> -
> - flash@0 {
> - compatible = "micron,n25q128a11", "jedec,spi-nor";
> - reg = <0>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - spi-max-frequency = <50000000>;
> - };
> -};
> -
> -&blsp1_uart2 {
> - pinctrl-0 = <&uart2_pins>;
> - pinctrl-names = "default";
> - status = "okay";
> -};
> -
> -&rpm_requests {
> - regulators {
> - compatible = "qcom,rpm-mp5496-regulators";
> -
> - ipq9574_s1: s1 {
> - /*
> - * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
> - * During regulator registration, kernel not knowing the initial voltage,
> - * considers it as zero and brings up the regulators with minimum supported voltage.
> - * Update the regulator-min-microvolt with SVS voltage of 725mV so that
> - * the regulators are brought up with 725mV which is sufficient for all the
> - * corner parts to operate at 800MHz
> - */
> - regulator-min-microvolt = <725000>;
> - regulator-max-microvolt = <1075000>;
> - };
> - };
> -};
> -
> -&sleep_clk {
> - clock-frequency = <32000>;
> -};
> -
> -&tlmm {
> - spi_0_pins: spi-0-state {
> - pins = "gpio11", "gpio12", "gpio13", "gpio14";
> - function = "blsp0_spi";
> - drive-strength = <8>;
> - bias-disable;
> - };
> -};
> -
> -&xo_board_clk {
> - clock-frequency = <24000000>;
> };
