On Fri, Jul 14, 2023 at 01:17:12PM -0500, Andrew Halaney wrote: > On Fri, Jul 14, 2023 at 11:40:09AM +0530, Ninad Naik wrote: > > SA8775 and newer target have added support for an increased number of > > interrupt targets. To implement this change, the intr_target field, which > > is used to configure the interrupt target in the interrupt configuration > > register is increased from 3 bits to 4 bits. > > > > In accordance to these updates, a new intr_target_width member is > > introduced in msm_pingroup structure. This member stores the value of > > width of intr_target field in the interrupt configuration register. This > > value is used to dynamically calculate and generate mask for setting the > > intr_target field. By default, this mask is set to 3 bit wide, to ensure > > backward compatibility with the older targets. > > > > Signed-off-by: Ninad Naik <quic_ninanaik@xxxxxxxxxxx> > > Thanks for the patch. Naive question (without really reading the code), > but what practical affect does this have? > > i.e. does this change behavior of how IRQs were handled before this > patch vs after on this platform? > Yes, the affected field denotes where interrupts should be routed and without this patch not all the bits where updated. > To shed some light on the question, there's a GPIO IRQ for the ethernet > phy on this platform that is purposely _not_ described because it didn't > ever trigger, resulting in the interface staying down. Things work > fine without the IRQ (the driver goes into polling mode). > The explanation I got was very brief and attributed it to a "hardware issue". > > I'm wondering if I should re-evaluate that, and if this was the > "hardware issue". > It's plausible that your interrupt fired elsewhere. Definitely worth giving that scenario another test run. Regards, Bjorn
