On Fri, Jul 14, 2023 at 11:40:09AM +0530, Ninad Naik wrote: > SA8775 and newer target have added support for an increased number of > interrupt targets. To implement this change, the intr_target field, which > is used to configure the interrupt target in the interrupt configuration > register is increased from 3 bits to 4 bits. > > In accordance to these updates, a new intr_target_width member is > introduced in msm_pingroup structure. This member stores the value of > width of intr_target field in the interrupt configuration register. This > value is used to dynamically calculate and generate mask for setting the > intr_target field. By default, this mask is set to 3 bit wide, to ensure > backward compatibility with the older targets. > > Signed-off-by: Ninad Naik <quic_ninanaik@xxxxxxxxxxx> Very nice, Ninad. Reviewed-by: Bjorn Andersson <quic_bjorande@xxxxxxxxxxx> > --- > drivers/pinctrl/qcom/pinctrl-msm.c | 9 ++++++--- > drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ > drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1 + > 3 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index 2585ef2b2793..6ebcaa2220af 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -1038,6 +1038,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) > struct gpio_chip *gc = irq_data_get_irq_chip_data(d); > struct msm_pinctrl *pctrl = gpiochip_get_data(gc); > const struct msm_pingroup *g; > + u32 intr_target_mask = 0x7; I like Konrad's suggestion about making this GENMASK(2, 0). Please update that and include our R-b tags in v2. Regards, Bjorn
