On 19.06.2023 18:18, Konrad Dybcio wrote:
> Apart from a total LLCC + APSS power collapse, SC8280XP can also put
> either the DSU rail (CPU + L3), or VDD_CX in power collapse.
>
> Add support for these lower idle states to allow more flexibility.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index ac0596dfdbc4..d524f851cb53 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -285,7 +285,23 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> };
>
> domain-idle-states {
> - CLUSTER_SLEEP_0: cluster-sleep-0 {
> + CLUSTER_SLEEP_L3_PC: cluster-sleep-0 {
I guess this is misleading.
cluster-sleep-0 would be APSS_OFF (cores and caches have no power)
cluster-sleep-1 is ok (the CX rail is 0.0W)
cluster-sleep-2 would be AOSS_SLEEP (a.k.a. we've entered the SLEEP
state within RPMh and the system needs to be woken up by PDC)
Konrad
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x41000044>;
> + entry-latency-us = <2752>;
> + exit-latency-us = <3048>;
> + min-residency-us = <6118>;
> + };
> +
> + CLUSTER_SLEEP_CX_OFF: cluster-sleep-1 {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x41002344>;
> + entry-latency-us = <3263>;
> + exit-latency-us = <4562>;
> + min-residency-us = <8467>;
> + };
> +
> + CLUSTER_SLEEP_APSS_OFF: cluster-sleep-2 {
> compatible = "domain-idle-state";
> arm,psci-suspend-param = <0x4100c344>;
> entry-latency-us = <3263>;
> @@ -632,7 +648,7 @@ CPU_PD7: power-domain-cpu7 {
>
> CLUSTER_PD: power-domain-cpu-cluster0 {
> #power-domain-cells = <0>;
> - domain-idle-states = <&CLUSTER_SLEEP_0>;
> + domain-idle-states = <&CLUSTER_SLEEP_L3_PC &CLUSTER_SLEEP_CX_OFF &CLUSTER_SLEEP_APSS_OFF>;
> };
> };
>
>
