On Wed, Jun 21, 2023 at 10:06:18AM +0530, Krishna Kurapati wrote: > Currently the DWC3 driver supports only single port controller which > requires at most two PHYs ie HS and SS PHYs. There are SoCs that has > DWC3 controller with multiple ports that can operate in host mode. > Some of the port supports both SS+HS and other port supports only HS > mode. > > This change primarily refactors the Phy logic in core driver to allow > multiport support with Generic Phy's. > > Chananges have been tested on QCOM SoC SA8295P which has 4 ports (2 > are HS+SS capable and 2 are HS only capable). > > Changes in v9: > Added IRQ support for DP/DM/SS MP Irq's of SC8280 > Refactored code to read port count by accessing xhci registers > You obviously did many more changes in v9. Please amend this list for v9 and be more specific when submitting v10. Johan
