On Sat, Jun 24, 2023 at 12:39:36AM +0200, Konrad Dybcio wrote:
> On 21.06.2023 06:36, Krishna Kurapati wrote:
> > Add USB and DWC3 node for tertiary port of SC8280 along with multiport
> > IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
> > platforms.
> >
> > Signed-off-by: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++++++++++++++++++++++++
> > 1 file changed, 77 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > index 8fa9fbfe5d00..0dfa350ea3b3 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > @@ -3013,6 +3013,83 @@ system-cache-controller@9200000 {
> > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> > };
> >
> > + usb_2: usb@a4f8800 {
> > + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
> > + reg = <0 0x0a4f8800 0 0x400>;
>
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> These three properties, please stick just before status
No, please keep them were they are for consistency with the rest of the
file.
> > +
> > + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
> > + <&gcc GCC_USB30_MP_MASTER_CLK>,
> > + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
> > + <&gcc GCC_USB30_MP_SLEEP_CLK>,
> > + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> > + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
> > + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
> > + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
> > + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
> > + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
> > + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
> Please make it one per line
Also not needed for the same reason.
>
> > +
> > + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> > + <&gcc GCC_USB30_MP_MASTER_CLK>;
> > + assigned-clock-rates = <19200000>, <200000000>;
> And here
Same here.
Johan
