On Tue, Jun 27, 2023 at 06:31:30AM +0530, Krishna chaitanya chundru wrote: > Add pcie-mem interconnect path to sdx65 target. > "target" is meaningless in upstream. Call it "SoC or platform". Also the subject should mention PCIe interconnect. > Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> With both changes above, Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > --- > arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi > index 1a35830..77fa97c 100644 > --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi > @@ -332,6 +332,9 @@ > <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "global", "doorbell"; > > + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; > + interconnect-names = "pcie-mem"; > + > resets = <&gcc GCC_PCIE_BCR>; > reset-names = "core"; > > -- > 2.7.4 > -- மணிவண்ணன் சதாசிவம்
