The PMIC is not a part of the SoC, so move PMIC to a separate file and
include it from the board files.
Suggested-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
arch/arm/boot/dts/qcom/pm8018.dtsi | 57 +++++++++++++++++++
.../boot/dts/qcom/qcom-mdm9615-wp8548.dtsi | 3 +-
arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi | 46 +--------------
3 files changed, 61 insertions(+), 45 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom/pm8018.dtsi
diff --git a/arch/arm/boot/dts/qcom/pm8018.dtsi b/arch/arm/boot/dts/qcom/pm8018.dtsi
new file mode 100644
index 000000000000..81c0ad29fe60
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/pm8018.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Device Tree Source for Qualcomm PM8018
+ *
+ * Copyright (C) 2016 BayLibre, SAS.
+ * Author : Neil Armstrong <narmstrong@xxxxxxxxxxxx>
+ */
+
+&ssbi {
+ pm8018: pmic {
+ compatible = "qcom,pm8018", "qcom,pm8921";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwrkey@1c {
+ compatible = "qcom,pm8018-pwrkey",
+ "qcom,pm8921-pwrkey";
+ reg = <0x1c>;
+ interrupt-parent = <&pm8018>;
+ interrupts = <50 IRQ_TYPE_EDGE_RISING>,
+ <51 IRQ_TYPE_EDGE_RISING>;
+ debounce = <15625>;
+ pull-up;
+ };
+
+ pm8018_mpps: mpps@50 {
+ compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
+ reg = <0x50>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8018_mpps 0 0 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ rtc@11d {
+ compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
+ reg = <0x11d>;
+ interrupt-parent = <&pm8018>;
+ interrupts = <39 IRQ_TYPE_EDGE_RISING>;
+ allow-set-time;
+ };
+
+ pm8018_gpio: gpio@150 {
+ compatible = "qcom,pm8058-gpio",
+ "qcom,ssbi-gpio";
+ reg = <0x150>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8018_gpio 0 0 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi
index 92c8003dac25..cc264861afe5 100644
--- a/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi
@@ -7,6 +7,7 @@
*/
#include "qcom-mdm9615.dtsi"
+#include "pm8018.dtsi"
/ {
model = "Sierra Wireless WP8548 Module";
@@ -76,7 +77,7 @@ reset-out-pins {
};
};
-&pmicgpio {
+&pm8018_gpio {
usb_vbus_5v_pins: usb-vbus-5v-state {
pins = "gpio4";
function = "normal";
diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi
index b40c52ddf9b4..ac2327bc4ec5 100644
--- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi
@@ -241,56 +241,14 @@ gsbi5_serial: serial@16440000 {
};
};
- qcom,ssbi@500000 {
+ ssbi: qcom,ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
- pmicintc: pmic {
- compatible = "qcom,pm8018", "qcom,pm8921";
+ pmic {
interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pwrkey@1c {
- compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
- reg = <0x1c>;
- interrupt-parent = <&pmicintc>;
- interrupts = <50 IRQ_TYPE_EDGE_RISING>,
- <51 IRQ_TYPE_EDGE_RISING>;
- debounce = <15625>;
- pull-up;
- };
-
- pmicmpp: mpps@50 {
- compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x50>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pmicmpp 0 0 6>;
- };
-
- rtc@11d {
- compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
- interrupt-parent = <&pmicintc>;
- interrupts = <39 IRQ_TYPE_EDGE_RISING>;
- reg = <0x11d>;
- allow-set-time;
- };
-
- pmicgpio: gpio@150 {
- compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
- reg = <0x150>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pmicgpio 0 0 6>;
- #gpio-cells = <2>;
- };
};
};
