The downsteam driver for dispcc only ever gets and puts this clock
without ever using it in the clocktree; this unnecessary workaround was
never ported to mainline, hence the driver doesn't consume this clock
and shouldn't be required by the bindings.
Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings")
Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
index 8a210c4c5f82..2acf487d8a2f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
@@ -28,7 +28,6 @@ properties:
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
- - description: AHB config clock from GCC
clock-names:
items:
@@ -38,7 +37,6 @@ properties:
- const: dsi1_phy_pll_out_dsiclk
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
- - const: cfg_ahb_clk
'#clock-cells':
const: 1
@@ -71,15 +69,13 @@ examples:
<&dsi0_phy 1>,
<&dsi1_phy 1>,
<&dp_phy 0>,
- <&dp_phy 1>,
- <&gcc GCC_DISP_AHB_CLK>;
+ <&dp_phy 1>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
- "dp_phy_pll_vco_div_clk",
- "cfg_ahb_clk";
+ "dp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#power-domain-cells = <1>;
};
--
2.41.0
