On 22.06.2023 11:27, AngeloGioacchino Del Regno wrote:
> Writing the new TTBRs, TCRs and MAIRs on a previously enabled
> context bank may trigger a context fault, resulting in firmware
> driven AP resets: change the domain initialization programming
> sequence to disable the context bank(s) and to also clear the
> related fault address (CB_FAR) and fault status (CB_FSR)
> registers before writing new values to TTBR0/1, TCR/TCR2, MAIR0/1.
>
> Fixes: 0ae349a0f33f ("iommu/qcom: Add qcom_iommu")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> index 8face57c4180..f1bd7c035db8 100644
> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> @@ -273,6 +273,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
> ctx->secure_init = true;
> }
>
> + /* Disable context bank before programming */
> + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
> +
> + /* Clear context bank fault address fault status registers */
> + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
> + iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
> +
> /* TTBRs */
> iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
> pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
