This series brings some niceties in preparation for A7xx introduction. It should be fully independent of the GMU wrapper series. Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> --- Changes in v4: - Fix an issue where half of patch 1 got squashed into the cover letter.. - Link to v3: https://lore.kernel.org/r/20230517-topic-a7xx_prep-v3-0-a3ce3725385b@xxxxxxxxxx Changes in v3: - Pull more definitions from mesa - Decode CP_PROTECT_CNTL bitfields - Rebase on next-20230619 - Link to v2: https://lore.kernel.org/r/20230517-topic-a7xx_prep-v2-0-5b9daa2b2cf0@xxxxxxxxxx Changes in v2: - Drop switching to using the GMU_AO counter in timestamp - Add a definition for REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, may be subbed with a register sync after mesa MR22901 - Link to v1: https://lore.kernel.org/r/20230517-topic-a7xx_prep-v1-0-7a964f2e99c2@xxxxxxxxxx --- Konrad Dybcio (6): drm/msm/a6xx: Add some missing header definitions drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTL drm/msm/a6xx: Skip empty protection ranges entries drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start drm/msm/a6xx: Improve GMU force shutdown sequence drm/msm/a6xx: Fix up GMU region reservations drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 +++++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++++++++++---- 4 files changed, 32 insertions(+), 8 deletions(-) --- base-commit: 9dbf40840551df336c95ce2a3adbdd25ed53c0ef change-id: 20230517-topic-a7xx_prep-787a69c7d0ff Best regards, -- Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
