On 2023-06-16 13:03:07, Dmitry Baryshkov wrote:
> Shift dpu_ctl_cfg contents to correct the indentation of CTL blocks.
> This is done in preparation to expanding the rest of hardware block
> defines, so that all blocks have similar indentation.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Reviewed-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 46 +++++++-------
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 46 +++++++-------
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 63 +++++++++----------
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 63 +++++++++----------
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 63 +++++++++----------
> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 30 +++++----
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 +--
> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 41 ++++++------
> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 +--
> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 8 +--
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 63 +++++++++----------
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 41 ++++++------
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 63 +++++++++----------
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 63 +++++++++----------
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 63 +++++++++----------
> 15 files changed, 309 insertions(+), 360 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index e0cc1ce3f3e2..6660a55909e7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -46,31 +46,27 @@ static const struct dpu_mdp_cfg msm8998_mdp = {
>
> static const struct dpu_ctl_cfg msm8998_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0x94,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x1200, .len = 0x94,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x1400, .len = 0x94,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x1600, .len = 0x94,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> - },
> - {
> - .name = "ctl_4", .id = CTL_4,
> - .base = 0x1800, .len = 0x94,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x94,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x94,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x94,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x94,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + }, {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x1800, .len = 0x94,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index f52e1fa27e2c..8f96a9e4ee4c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -44,31 +44,27 @@ static const struct dpu_mdp_cfg sdm845_mdp = {
>
> static const struct dpu_ctl_cfg sdm845_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0xe4,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x1200, .len = 0xe4,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x1400, .len = 0xe4,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x1600, .len = 0xe4,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> - },
> - {
> - .name = "ctl_4", .id = CTL_4,
> - .base = 0x1800, .len = 0xe4,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0xe4,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0xe4,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0xe4,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0xe4,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + }, {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x1800, .len = 0xe4,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 6e6b4368e254..7a37e9ef3085 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8150_mdp = {
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> static const struct dpu_ctl_cfg sm8150_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x1200, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x1400, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x1600, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> - },
> - {
> - .name = "ctl_4", .id = CTL_4,
> - .base = 0x1800, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> - },
> - {
> - .name = "ctl_5", .id = CTL_5,
> - .base = 0x1a00, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + }, {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x1800, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + }, {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a00, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index b22e82919395..9e288d849a8a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -44,40 +44,35 @@ static const struct dpu_mdp_cfg sc8180x_mdp = {
>
> static const struct dpu_ctl_cfg sc8180x_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x1200, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x1400, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x1600, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> - },
> - {
> - .name = "ctl_4", .id = CTL_4,
> - .base = 0x1800, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> - },
> - {
> - .name = "ctl_5", .id = CTL_5,
> - .base = 0x1a00, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + }, {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x1800, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + }, {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a00, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index e321cc0a80ee..82adbdaba472 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8250_mdp = {
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> static const struct dpu_ctl_cfg sm8250_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x1200, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x1400, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x1600, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> - },
> - {
> - .name = "ctl_4", .id = CTL_4,
> - .base = 0x1800, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> - },
> - {
> - .name = "ctl_5", .id = CTL_5,
> - .base = 0x1a00, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + }, {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x1800, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + }, {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a00, .len = 0x1e0,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 1919ee487e68..a7f067f4c4ba 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -36,22 +36,20 @@ static const struct dpu_mdp_cfg sc7180_mdp = {
>
> static const struct dpu_ctl_cfg sc7180_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x1200, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x1400, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 0252fe9590e7..2cf3ed980582 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -34,10 +34,10 @@ static const struct dpu_mdp_cfg sm6115_mdp = {
>
> static const struct dpu_ctl_cfg sm6115_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 3c2083760294..4ba2f7acf8b7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -39,28 +39,25 @@ static const struct dpu_mdp_cfg sm6350_mdp = {
>
> static const struct dpu_ctl_cfg sm6350_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x1200, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x1400, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x1600, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 54cc6ad8ee36..3094f4dc6a76 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -31,10 +31,10 @@ static const struct dpu_mdp_cfg qcm2290_mdp = {
>
> static const struct dpu_ctl_cfg qcm2290_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index f0f6f2d801b4..e9c63eeb280f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -35,10 +35,10 @@ static const struct dpu_mdp_cfg sm6375_mdp = {
>
> static const struct dpu_ctl_cfg sm6375_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 318bed612da5..8e63d6f310c2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -43,40 +43,35 @@ static const struct dpu_mdp_cfg sm8350_mdp = {
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> static const struct dpu_ctl_cfg sm8350_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x15000, .len = 0x1e8,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x16000, .len = 0x1e8,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x17000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x18000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> - },
> - {
> - .name = "ctl_4", .id = CTL_4,
> - .base = 0x19000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> - },
> - {
> - .name = "ctl_5", .id = CTL_5,
> - .base = 0x1a000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x15000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x16000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x17000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x18000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + }, {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x19000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + }, {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index ca5bf4ad2444..783deae7c1c4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -37,28 +37,25 @@ static const struct dpu_mdp_cfg sc7280_mdp = {
>
> static const struct dpu_ctl_cfg sc7280_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x15000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x16000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x17000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x18000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x15000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x16000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x17000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x18000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index e645dd1f418f..db4d6643c0dd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sc8280xp_mdp = {
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x15000, .len = 0x204,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x16000, .len = 0x204,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x17000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x18000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> - },
> - {
> - .name = "ctl_4", .id = CTL_4,
> - .base = 0x19000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> - },
> - {
> - .name = "ctl_5", .id = CTL_5,
> - .base = 0x1a000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x15000, .len = 0x204,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x16000, .len = 0x204,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x17000, .len = 0x204,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x18000, .len = 0x204,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + }, {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x19000, .len = 0x204,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + }, {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a000, .len = 0x204,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 55b0cfa2b205..8fdf55c25b9f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8450_mdp = {
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> static const struct dpu_ctl_cfg sm8450_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x15000, .len = 0x204,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x16000, .len = 0x204,
> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x17000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x18000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> - },
> - {
> - .name = "ctl_4", .id = CTL_4,
> - .base = 0x19000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> - },
> - {
> - .name = "ctl_5", .id = CTL_5,
> - .base = 0x1a000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x15000, .len = 0x204,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x16000, .len = 0x204,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x17000, .len = 0x204,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x18000, .len = 0x204,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + }, {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x19000, .len = 0x204,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + }, {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a000, .len = 0x204,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index aef533b81cbe..8d733ef606b9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -46,40 +46,35 @@ static const struct dpu_mdp_cfg sm8550_mdp = {
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> static const struct dpu_ctl_cfg sm8550_ctl[] = {
> {
> - .name = "ctl_0", .id = CTL_0,
> - .base = 0x15000, .len = 0x290,
> - .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> - },
> - {
> - .name = "ctl_1", .id = CTL_1,
> - .base = 0x16000, .len = 0x290,
> - .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> - },
> - {
> - .name = "ctl_2", .id = CTL_2,
> - .base = 0x17000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> - },
> - {
> - .name = "ctl_3", .id = CTL_3,
> - .base = 0x18000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> - },
> - {
> - .name = "ctl_4", .id = CTL_4,
> - .base = 0x19000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> - },
> - {
> - .name = "ctl_5", .id = CTL_5,
> - .base = 0x1a000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x15000, .len = 0x290,
> + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + }, {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x16000, .len = 0x290,
> + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + }, {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x17000, .len = 0x290,
> + .features = CTL_SM8550_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + }, {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x18000, .len = 0x290,
> + .features = CTL_SM8550_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + }, {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x19000, .len = 0x290,
> + .features = CTL_SM8550_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + }, {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a000, .len = 0x290,
> + .features = CTL_SM8550_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
>
> --
> 2.39.2
>
