On Thu, 01 Jun 2023 11:39:06 +0200, Konrad Dybcio wrote:
> Some recent-ish clock drivers touching on the "standard" Alpha PLLs
> have been specifying the values that should be written into the CTL
> registers as mask-value combos, but that wasn't always reflected
> properly (or at all). This series tries to fix that without affecitng
> the drivers that actually provide the full register values.
>
>
> [...]
Applied, thanks!
[1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
commit: 501624339466a7896bb8a1f048cf8dcfd54b174e
[2/2] clk: qcom: gcc-sm6115: Add missing PLL config properties
commit: e88c533d8a2a0fe84bb54cff1569bd079ad3512c
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
