On Mon, Jun 12, 2023 at 08:39:04AM +0300, Dmitry Baryshkov wrote: > Implement CPUFreq support for one of the oldest supported Qualcomm > platforms, APQ8064. Each core has independent power and frequency > control. Additionally the L2 cache is scaled to follow the CPU > frequencies (failure to do so results in strange semi-random crashes). Hi, can we talk, maybe in private about this interconnect-cpu thing? I see you follow the original implementation of the msm_bus where in practice with the use of the kbps the correct clock and voltage was set. (and this was also used to set the fabric clock from nominal to fast) On ipq806x and I assume other SoC there isn't always a 1:1 map of CPU freq and L2 freq. For example on ipq8064 we have max CPU freq of 1.4GHz and L2 freq of 1.2GHz, on ipq8065 we have CPU 1.7GHz and L2 of 1.4GHz. (and even that is curious since I used the debug regs and the cxo crystal to measure the clock by hardware (yes i ported the very ancient clk-debug to modern kernel and it works and discovered all sort of things) the L2 (I assume due to climitation of the hfpll) actually can't never reach that frequency (1.4GHz in reality results to something like 1.2GHz from what I notice a stable clock is there only with frequency of max 1GHz)) So my idea was to introduce a simple devfreq driver and use the PASSIVE governor where it was added the possibility to link to a CPU frequency and with interpolation select the L2 frequency (and voltage) >From some old comments in ancient qsdk code it was pointed out that due to a hw limitation the secondary cpu can't stay at a high clock if L2 was at the idle clock. (no idea if this is specific to IPQ806x) So this might be a cause of your crash? (I also have random crash with L2 scaling and we are planning to just force the L2 at max frequency) But sorry for all of this (maybe) useless info. I checked the other patch and I didn't understand how the different L2 frequency are declared and even the voltage. Is this something that will come later? I'm very interested in this implementation. > > Core voltage is controlled through the SAW2 devices, one for each core. > The L2 has two regulators, vdd-mem and vdd-dig. > > Depenency: [1] for interconnect-clk implementation > > https://lore.kernel.org/linux-arm-msm/20230512001334.2983048-3-dmitry.baryshkov@xxxxxxxxxx/ > -- Ansuel
