On 6.06.2023 22:26, Stephan Gerhold wrote:
> On Tue, Jun 06, 2023 at 06:15:28PM +0200, Konrad Dybcio wrote:
>> Add the (scarce) idle states for the individual CPUs, as well as the
>> whole cluster. This enables deeper-than-WFI cpuidle
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 61 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 61 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>> index b29bc4e4b837..a8a1ce58c0b7 100644
>> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>> @@ -48,6 +48,8 @@ CPU0: cpu@0 {
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> L2_0: l2-cache {
>> compatible = "cache";
>> cache-level = <2>;
>> @@ -65,6 +67,8 @@ CPU1: cpu@1 {
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> + power-domains = <&CPU_PD1>;
>> + power-domain-names = "psci";
>> };
>>
>> CPU2: cpu@2 {
>> @@ -77,6 +81,8 @@ CPU2: cpu@2 {
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> + power-domains = <&CPU_PD2>;
>> + power-domain-names = "psci";
>> };
>>
>> CPU3: cpu@3 {
>> @@ -89,6 +95,8 @@ CPU3: cpu@3 {
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> + power-domains = <&CPU_PD3>;
>> + power-domain-names = "psci";
>> };
>>
>> cpu-map {
>> @@ -110,6 +118,30 @@ core3 {
>> };
>> };
>> };
>> +
>> + domain-idle-states {
>> + CLUSTER_SLEEP: cluster-sleep-0 {
>> + compatible = "domain-idle-state";
>> + arm,psci-suspend-param = <0x40000044>;
>
> Are you sure this is correct? Based on lpm-levels/scuba-pm downstream
> I would expect:
>
> - That the CPU mode part (last digit) is equal to the deepest per-CPU
> state (0x3) and only the cluster mode part (digit before) changes
> - That you pass the "last in power level" needed for OSI in << 24
0x3 I agree (though by luck it turns out that 0x4 is also implemented!)
BIT(24) - right, the firmware could fail to power off the shared cluster
resources (like Ln$) with that missing.. Thanks for catching this!
Konrad
>
> Some of the numbers in sm6115.dtsi also look suspicious if you want to
> recheck those...
>
> Thanks,
> Stephan
