On 1.06.2023 16:07, Neil Armstrong wrote:
> Add the USB3+DP Combo QMP PHY port subnodes in the SM8550 SoC DTSI
> to avoid duplication in the devices DTs.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index b41b3981b3ce..ca2280041f83 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -2838,6 +2838,32 @@ usb_dp_qmpphy: phy@88e8000 {
> #phy-cells = <1>;
>
> status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_dp_qmpphy_out: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_dp_qmpphy_usb_ss_in: endpoint {
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + usb_dp_qmpphy_dp_in: endpoint {
> + };
> + };
> + };
> };
>
> usb_1: usb@a6f8800 {
>
