Add zeroth and third instance of the QUPv3 engine to the sa8775p.dtsi.
Signed-off-by: Shazad Hussain <quic_shazhuss@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index fbe98ff1bcf8..27af8386a3f8 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -568,6 +568,19 @@
};
};
+ qupv3_id_0: geniqup@9c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x9c0000 0x0 0x6000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x403 0x0>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -612,6 +625,19 @@
};
};
+ qupv3_id_3: geniqup@bc0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0xbc0000 0x0 0x6000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x43 0x0>;
+ status = "disabled";
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
--
2.17.1
