On 21.05.2023 22:23, Dmitry Baryshkov wrote:
> Change the USB QMP PHY to use newer style of QMP PHY bindings (single
> resource region, no per-PHY subnodes).
>
> Reviewed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 57 ++++++++++------------------
> 1 file changed, 19 insertions(+), 38 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index ea1ffade1aa1..b07a49e6829a 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -14,6 +14,7 @@
> #include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/interconnect/qcom,sc7180.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> #include <dt-bindings/phy/phy-qcom-qusb2.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/reset/qcom,sdm845-aoss.h>
> @@ -2718,49 +2719,28 @@ usb_1_hsphy: phy@88e3000 {
> nvmem-cells = <&qusb2p_hstx_trim>;
> };
>
> - usb_1_qmpphy: phy-wrapper@88e9000 {
> + usb_1_qmpphy: phy@88e8000 {
> compatible = "qcom,sc7180-qmp-usb3-dp-phy";
> - reg = <0 0x088e9000 0 0x18c>,
> - <0 0x088e8000 0 0x3c>,
> - <0 0x088ea000 0 0x18c>;
> + reg = <0 0x088e8000 0 0x3000>;
> status = "disabled";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
>
> clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> - clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
> + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
These are unaligned
Other than that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "usb3_pipe",
> + "cfg_ahb";
>
> resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> reset-names = "phy", "common";
>
> - usb_1_ssphy: usb3-phy@88e9200 {
> - reg = <0 0x088e9200 0 0x128>,
> - <0 0x088e9400 0 0x200>,
> - <0 0x088e9c00 0 0x218>,
> - <0 0x088e9600 0 0x128>,
> - <0 0x088e9800 0 0x200>,
> - <0 0x088e9a00 0 0x18>;
> - #clock-cells = <0>;
> - #phy-cells = <0>;
> - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> - clock-names = "pipe0";
> - clock-output-names = "usb3_phy_pipe_clk_src";
> - };
> -
> - dp_phy: dp-phy@88ea200 {
> - reg = <0 0x088ea200 0 0x200>,
> - <0 0x088ea400 0 0x200>,
> - <0 0x088eaa00 0 0x200>,
> - <0 0x088ea600 0 0x200>,
> - <0 0x088ea800 0 0x200>;
> - #clock-cells = <1>;
> - #phy-cells = <0>;
> - };
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> };
>
> dc_noc: interconnect@9160000 {
> @@ -2840,7 +2820,7 @@ usb_1_dwc3: usb@a600000 {
> iommus = <&apps_smmu 0x540 0>;
> snps,dis_u2_susphy_quirk;
> snps,dis_enblslpm_quirk;
> - phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
> phy-names = "usb2-phy", "usb3-phy";
> maximum-speed = "super-speed";
> };
> @@ -3148,8 +3128,9 @@ mdss_dp: displayport-controller@ae90000 {
> "ctrl_link_iface", "stream_pixel";
> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> - assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
> - phys = <&dp_phy>;
> + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> phy-names = "dp";
>
> operating-points-v2 = <&dp_opp_table>;
> @@ -3206,8 +3187,8 @@ dispcc: clock-controller@af00000 {
> <&gcc GCC_DISP_GPLL0_CLK_SRC>,
> <&dsi_phy 0>,
> <&dsi_phy 1>,
> - <&dp_phy 0>,
> - <&dp_phy 1>;
> + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> clock-names = "bi_tcxo",
> "gcc_disp_gpll0_clk_src",
> "dsi0_phy_pll_out_byteclk",
