On Mon, 22 May 2023 at 20:49, Yassine Oudjana <yassine.oudjana@xxxxxxxxx> wrote:
>
>
> On Wed, May 3 2023 at 04:20:00 PM +03:00:00, Dmitry Baryshkov
> <dmitry.baryshkov@xxxxxxxxxx> wrote:
> > On Wed, 3 May 2023 at 16:02, Yassine Oudjana
> > <yassine.oudjana@xxxxxxxxx> wrote:
> >>
> >> From: Yassine Oudjana <y.oudjana@xxxxxxxxxxxxxx>
> >>
> >> The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2.
> >> Handle the
> >> difference accordingly.
> >>
> >> Signed-off-by: Yassine Oudjana <y.oudjana@xxxxxxxxxxxxxx>
> >> ---
> >> drivers/clk/qcom/clk-cbf-8996.c | 121
> >> ++++++++++++++++++++++++++++----
> >> 1 file changed, 106 insertions(+), 15 deletions(-)
> >>
> >> diff --git a/drivers/clk/qcom/clk-cbf-8996.c
> >> b/drivers/clk/qcom/clk-cbf-8996.c
> >> index 1bb2cd956d68..a3e96578ddd9 100644
> >> --- a/drivers/clk/qcom/clk-cbf-8996.c
> >> +++ b/drivers/clk/qcom/clk-cbf-8996.c
> >> @@ -65,6 +65,19 @@ static const struct alpha_pll_config
> >> cbfpll_config = {
> >> .early_output_mask = BIT(3),
> >> };
> >>
> >> +static const struct alpha_pll_config cbfpll_pro_config = {
> >> + .l = 72,
> >> + .config_ctl_val = 0x200d4828,
> >> + .config_ctl_hi_val = 0x006,
> >> + .test_ctl_val = 0x1c000000,
> >> + .test_ctl_hi_val = 0x00004000,
> >> + .pre_div_mask = BIT(12),
> >> + .post_div_mask = 0x3 << 8,
> >> + .post_div_val = 0x3 << 8,
> >> + .main_output_mask = BIT(0),
> >> + .early_output_mask = BIT(3),
> >> +};
> >
> > Granted that the difference between this and the non-pro is just the
> > post_div_val, would it be easier to just patch it in the probe()?
>
> I wasn't sure if that approach would've been accepted since it relies
> on the special case that only one instance of the CBF device will exist
> in normal conditions, but if you say it's fine then sure, I can do that.
We do this for other clock controllers, which we know to be singleton.
So this should be fine too.
--
With best wishes
Dmitry
