On 12.05.2023 23:17, Dmitry Baryshkov wrote:
> The pll0_vote clock definitely should have pll0 as a parent (instead of
> pll8).
>
> Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers")
> Cc: stable@xxxxxxxxxx
> Reviewed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> drivers/clk/qcom/gcc-mdm9615.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> index fb5c1244fb97..2f921891008d 100644
> --- a/drivers/clk/qcom/gcc-mdm9615.c
> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> @@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "pll0_vote",
> - .parent_names = (const char *[]){ "pll8" },
> + .parent_names = (const char *[]){ "pll0" },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
