On 2023-04-26 12:11:39, Abhinav Kumar wrote: > > > On 4/26/2023 12:08 PM, Marijn Suijten wrote: > > On 2023-04-26 09:24:19, Abhinav Kumar wrote: > >> > >> > >> On 4/25/2023 4:05 PM, Marijn Suijten wrote: > >>> According to downstream sources this DITHER sub-block sits at an offset > >>> of 0xe0 with version 0x20000. The PP_BLK_DITHER macro is _not_ used as > >>> downstream still says the size of the PINGPONG block is 0xd4 and not 0. > >>> > >> > >> the PINGPONG block size is 0x0 on sm8350, sm8450 and sc8280xp. > >> > >> and length of dither is 0x20 and they all start at 0xe0. > >> > >> So now does anything prevent us from using PP_BLK_DITHER macro for these? > > > > Nothing prevents it from being used (if you are referring to our > > previous conversations) besides this information not being available in > > public DTS (I simply did not know) and the fact that all these many > > fixes - however necessary they are - distract from the main topic of > > this series: bringing INTF TE support to DPU1. > > > > Yeah, you could have sent these as a separate series if you wanted to > stick to this one being only intf te. As already explained in IRC, and repeating here for posterity: Maintaining two heavily-dependent series that constantly touch the exact same lines in the catalog for many SoCs at once is pretty much impossible. Doing it that way relies on one of the two series to be easily pick-able so that the other can proceed through a few review rounds and revisions without constantly conflicting or having to be rebased on the other. And that doesn't apply here: both INTF TE and the fixes have required extra revisions. And then, some of the fixes are even preliminary to INTF TE support. - Marijn
