On 14.04.2023 22:54, Dmitry Baryshkov wrote: > Correct sm8350 PCIe PHY tables according to the vendor dtsi file. > This accounts some additional differences between PHY programming on > sm8350 and sm8450. > > The name for the PCS register 0x8 is not present in the vendor kernels, > but since on other generations the register prior to POWER_STATE_CONFIG2 > is called POWER_STATE_CONFIG1, we can establish that as its name. > > Fixes: c70052739d16 ("phy: qcom-qmp-pcie: add support for sm8350 platform") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > --- Are you referencing the entries in lahaina-2.1.dtsi? [...] > +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_pcs_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xa8), e.g. my downstream says 0x77 here > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), Konrad > +}; > + > +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_pcs_misc_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG1, 0x0f), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), > +}; > + > +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_serdes_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), > }; > > static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { > @@ -2325,15 +2349,15 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { > .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), > .rx = sm8450_qmp_gen3_pcie_rx_tbl, > .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), > - .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, > - .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), > - .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, > - .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), > + .pcs = sm8350_qmp_gen3x1_pcie_pcs_tbl, > + .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_pcs_tbl), > + .pcs_misc = sm8350_qmp_gen3x1_pcie_pcs_misc_tbl, > + .pcs_misc_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_pcs_misc_tbl), > }, > > .tbls_rc = &(const struct qmp_phy_cfg_tbls) { > - .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, > - .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), > + .serdes = sm8350_qmp_gen3x1_pcie_rc_serdes_tbl, > + .serdes_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_serdes_tbl), > .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, > .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), > }, > @@ -2369,6 +2393,8 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { > }, > > .tbls_rc = &(const struct qmp_phy_cfg_tbls) { > + .serdes = sm8350_qmp_gen3x2_pcie_rc_serdes_tbl, > + .serdes_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_serdes_tbl), > .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, > .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), > .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > index a469ae2a10a1..ea466e14ca12 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > @@ -8,6 +8,7 @@ > #define QCOM_PHY_QMP_PCS_PCIE_V5_H_ > > /* Only for QMP V5 PHY - PCS_PCIE registers */ > +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG1 0x08 > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 > #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20