On 16.04.2023 14:37, Krzysztof Kozlowski wrote: > The SM8550 DTSI defines a fixed PCIE1 PHY AUX clock and expects boards > to define frequency. Use the same as in MTP8550 to fix: > > sm8550-qrd.dtb: pcie-1-phy-aux-clk: 'clock-frequency' is a required property > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> Konrad > arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > index d5a645ee2a61..a08aa438bba8 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > @@ -359,6 +359,10 @@ vreg_l3g_1p2: ldo3 { > }; > }; > > +&pcie_1_phy_aux_clk { > + clock-frequency = <1000>; > +}; > + > &qupv3_id_0 { > status = "okay"; > };