On 4/11/2023 3:14 PM, Marijn Suijten wrote:
Full-caps DSC in the title, as discussed previously.
On that note, don't forget to CC those who have reviewed your patches
previously, as also brought up in earlier review.
On 2023-04-11 14:04:55, Kuogee Hsieh wrote:
In current code, the dsc active bits are set only if the cfg->dsc is set.
Some typo nits:
DSC* active bits.
s/are set/are written/ (the variable is set, registers are written).
Drop `the` before `cfg->dsc` (and you could replace `s/is set/is
non-zero/).
However, for displays which are hot-pluggable, there can be a use-case
of disconnecting a DSC supported sink and connecting a non-DSC sink.
For those cases we need to clear DSC active bits during teardown.
Fixes: ede3c6bb00c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl")
Signed-off-by: Kuogee Hsieh <quic_khsieh@xxxxxxxxxxx>
If you have validated that it is fine to write these registers on
_every_ platform supported by DPU1, and after fixing the above nits and
the Fixes: commit hash as pointed out by Abhinav:
Reviewed-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
And see one question below.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index bbdc95c..88e4efe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -541,10 +541,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
BIT(cfg->merge_3d - MERGE_3D_0));
- if (cfg->dsc) {
- DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX);
- DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
- }
+
+ DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX);
Does this flush all DSCs programmed in CTL_DSC_FLUSH as set above? That
is currently still in `if (cfg->dsc)` and never overwritten if all DSCs
are disabled, should it be taken out of the `if` to make sure no DSCs
are inadvertently flushed, or otherwise cache the "previous mask" to
make sure we flush exactly the right DSC blocks?
Yes, DSC flush is hierarchical. This is the main DSC flush which will
enforce the flush of the DSC's we are trying to flush in the
CTL_DSC_FLUSH register.
So if DSC was active, the CTL_FLUSH will only enforce the flush of the
DSC's programmed in CTL_DSC_FLUSH
If DSC is not active, we still need to flush that as well (that was the
missing bit).
No need to cache previous mask. That programming should be accurate in
cfg->dsc already.
Thanks!
- Marijn
+ DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
}
static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
--
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