On 11/04/2023 03:57, Abhinav Kumar wrote:
On 4/7/2023 5:27 PM, Dmitry Baryshkov wrote:
On sm8450 platform the CTL_0 doesn't differ from the rest of CTL blocks,
so switch it to CTL_SC7280_MASK too.
Some background: original commit 100d7ef6995d ("drm/msm/dpu: add support
for SM8450") had all (relevant at that time) bit spelled individually.
Then commit 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog"),
despite being a mismerge, correctly changed all other CTL entries to use
CTL_SC7280_MASK, except CTL_0.
While the current BLOCK_SOC_MASK style is not ideal (and while we are
working on a better scheme), let's follow its usage as a least minimal
surprise. For example, sc8280xp, a close associate of sm8450, also uses
CTL_SC7280_MASK.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
Although I dont totally agree with this, but because sc8280xp also uses
the same, I am fine.
Reviewed-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
But either we need to work on a better scheme or expand the macros but
not duplicate these for the next chipset which gets added.
Yes. I'm also holding the rest of MASK renaming patches for now.
I'd like to the following major items finalized and merged (probably a
goal for 6.5):
- INTF_TE restructure
- QSEED3/4 refactoring
- Proper support for active CTLs (wip), removing the need for
DPU_CTL_SPLIT_DISPLAY on sm8150+
- Pending platforms (2 from 6.x, one from 5.x, hopefully one from 4.x
too, 3.x if possible). Hopefully this will also include more platforms
from recent DPU generations (8.x, 9.x)
- Ideally: also sort out max SSPP line widths for VIG vs DMA
I think that after this we can return to the question of platform
similarities and differences.
Anyway, with the current msm-next + this patchset we should have a
catalog which one can expand without fearing about conflicts or
incorrect data duplication.
--
With best wishes
Dmitry
