PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices are found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. This series adds support for enabling the same DTS patch is based on the below series https://lore.kernel.org/linux-arm-msm/20230329053726.14860-1-quic_kathirav@xxxxxxxxxxx/ Changes in V2: - Reordered the patches and splitted the board DT changes into a separate patch as suggested - Detailed change logs are added to the respective patches Devi Priya (9): dt-bindings: clock: Add PCIe pipe clock definitions clk: qcom: gcc-ipq9574: Add PCIe pipe clocks dt-bindings: phy: qcom,qmp-pcie: Add ipq9574 bindings phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEs dt-bindings: PCI: qcom: Add IPQ9574 dt-bindings: pinctrl: qcom: Add few missing functions arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllers PCI: qcom: Add support for IPQ9574 .../devicetree/bindings/pci/qcom,pcie.yaml | 48 +++ .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 103 ++++- .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml | 6 +- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 62 +++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 375 +++++++++++++++++- drivers/clk/qcom/gcc-ipq9574.c | 76 ++++ drivers/pci/controller/dwc/pcie-qcom.c | 62 ++- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 332 ++++++++++++++++ .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 26 +- .../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 3 + include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 + 11 files changed, 1046 insertions(+), 51 deletions(-) base-commit: 31bd35b66249699343d2416658f57e97314a433a -- 2.17.1
