CMB_TIER register is CMB subunit timestamp insertion enable register.
Bit 0 is PATT_TSENAB bit. Set this bit to 1 to request a timestamp
following a CMB interface pattern match. Bit 1 is XTRIG_TSENAB bit.
Set this bit to 1 to request a timestamp following a CMB CTI timestamp
request. Bit 2 is TS_ALL bit. Set this bit to 1 to request timestamp
for all packets.
Signed-off-by: Mao Jinlong <quic_jinlmao@xxxxxxxxxxx>
---
.../testing/sysfs-bus-coresight-devices-tpdm | 24 ++++
drivers/hwtracing/coresight/coresight-tpdm.c | 114 ++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++
3 files changed, 152 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
index 4cc22ad5c485..aa357f463d03 100644
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
@@ -188,3 +188,27 @@ KernelVersion 6.3
Contact: Jinlong Mao <quic_jinlmao@xxxxxxxxxxx>
Description: (RW) Read or write the value of CMB subunit trigger pattern match.
+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt_ts
+Date: March 2023
+KernelVersion 6.3
+Contact: Jinlong Mao <quic_jinlmao@xxxxxxxxxxx>
+Description: (RW) Read or write status of timestamp upon CMB interface pattern match.
+ Only value 0 and 1 can be written to this node. Set this node to 1 to
+ request a timestamp following a CMB interface pattern match.
+
+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts
+Date: March 2023
+KernelVersion 6.3
+Contact: Jinlong Mao <quic_jinlmao@xxxxxxxxxxx>
+Description: (RW) Read or write the status of timestamp upon CMB cross trigger interface.
+ Only value 0 and 1 can be written to this node. Set this node to 1 to
+ request a timestamp following a CMB CTI timestamp request.
+
+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all
+Date: March 2023
+KernelVersion 6.3
+Contact: Jinlong Mao <quic_jinlmao@xxxxxxxxxxx>
+Description: (RW) Read or write the status of timestamp upon all interface.
+ Only value 0 and 1 can be written to this node. Set this node to 1 to requeset
+ timestamp to all trace packet.
+
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
index 05341fa7a6b7..88bb740cddd6 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.c
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -190,6 +190,22 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)
drvdata->base + TPDM_CMB_XPMR(i));
}
+ /* Configure timestamp control register. */
+ val = readl_relaxed(drvdata->base + TPDM_CMB_TIER);
+ if (drvdata->cmb->patt_ts)
+ val = val | TPDM_CMB_TIER_PATT_TSENAB;
+ else
+ val = val & ~TPDM_CMB_TIER_PATT_TSENAB;
+ if (drvdata->cmb->trig_ts)
+ val = val | TPDM_CMB_TIER_XTRIG_TSENAB;
+ else
+ val = val & ~TPDM_CMB_TIER_XTRIG_TSENAB;
+ if (drvdata->cmb->ts_all)
+ val = val | TPDM_CMB_TIER_TS_ALL;
+ else
+ val = val & ~TPDM_CMB_TIER_TS_ALL;
+ writel_relaxed(val, drvdata->base + TPDM_CMB_TIER);
+
val = readl_relaxed(drvdata->base + TPDM_CMB_CR);
/*
* Set to 0 for continuous CMB collection mode,
@@ -1048,6 +1064,101 @@ static ssize_t cmb_trig_patt_mask_store(struct device *dev,
}
static DEVICE_ATTR_RW(cmb_trig_patt_mask);
+static ssize_t cmb_patt_ts_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+
+ return scnprintf(buf, PAGE_SIZE, "%u\n",
+ (unsigned int)drvdata->cmb->patt_ts);
+}
+
+static ssize_t cmb_patt_ts_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (kstrtoul(buf, 16, &val) || (val & ~1UL))
+ return -EINVAL;
+
+ spin_lock(&drvdata->spinlock);
+ if (val)
+ drvdata->cmb->patt_ts = true;
+ else
+ drvdata->cmb->patt_ts = false;
+ spin_unlock(&drvdata->spinlock);
+ return size;
+}
+static DEVICE_ATTR_RW(cmb_patt_ts);
+
+static ssize_t cmb_ts_all_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+
+ return scnprintf(buf, PAGE_SIZE, "%u\n",
+ (unsigned int)drvdata->cmb->ts_all);
+}
+
+static ssize_t cmb_ts_all_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (kstrtoul(buf, 16, &val) || (val & ~1UL))
+ return -EINVAL;
+
+ spin_lock(&drvdata->spinlock);
+ if (val)
+ drvdata->cmb->ts_all = true;
+ else
+ drvdata->cmb->ts_all = false;
+ spin_unlock(&drvdata->spinlock);
+ return size;
+}
+static DEVICE_ATTR_RW(cmb_ts_all);
+
+static ssize_t cmb_trig_ts_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ return scnprintf(buf, PAGE_SIZE, "%u\n",
+ (unsigned int)drvdata->cmb->trig_ts);
+}
+
+static ssize_t cmb_trig_ts_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (kstrtoul(buf, 16, &val) || (val & ~1UL))
+ return -EINVAL;
+
+ spin_lock(&drvdata->spinlock);
+ if (val)
+ drvdata->cmb->trig_ts = true;
+ else
+ drvdata->cmb->trig_ts = false;
+ spin_unlock(&drvdata->spinlock);
+ return size;
+}
+static DEVICE_ATTR_RW(cmb_trig_ts);
+
static struct attribute *tpdm_dsb_attrs[] = {
&dev_attr_dsb_mode.attr,
&dev_attr_dsb_edge_ctrl.attr,
@@ -1070,6 +1181,9 @@ static struct attribute *tpdm_cmb_attrs[] = {
&dev_attr_cmb_patt_mask.attr,
&dev_attr_cmb_trig_patt_val.attr,
&dev_attr_cmb_trig_patt_mask.attr,
+ &dev_attr_cmb_patt_ts.attr,
+ &dev_attr_cmb_ts_all.attr,
+ &dev_attr_cmb_trig_ts.attr,
NULL,
};
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
index 616b6df41e00..88ade2f2ef6c 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.h
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h
@@ -12,6 +12,8 @@
/* CMB Subunit Registers*/
/*CMB subunit global control register*/
#define TPDM_CMB_CR (0xA00)
+/*CMB subunit timestamp insertion enable register*/
+#define TPDM_CMB_TIER (0xA04)
/*CMB subunit timestamp pattern registers*/
#define TPDM_CMB_TPR(n) (0xA08 + (n * 4))
/*CMB subunit timestamp pattern mask registers*/
@@ -25,6 +27,12 @@
#define TPDM_CMB_CR_ENA BIT(0)
/* Trace collection mode for CMB subunit*/
#define TPDM_CMB_CR_MODE BIT(1)
+/* Timestamp control for pattern match */
+#define TPDM_CMB_TIER_PATT_TSENAB BIT(0)
+/* CMB CTI timestamp request */
+#define TPDM_CMB_TIER_XTRIG_TSENAB BIT(1)
+/* For timestamp fo all trace*/
+#define TPDM_CMB_TIER_TS_ALL BIT(2)
/*Patten register number*/
#define TPDM_CMB_MAX_PATT 2
@@ -137,6 +145,9 @@ struct dsb_dataset {
* @patt_mask: Save value for pattern mask
* @trig_patt_val: Save value for trigger pattern
* @trig_patt_mask: Save value for trigger pattern mask
+ * @patt_ts: Indicates if pattern match for timestamp is enabled.
+ * @trig_ts: Indicates if CTI trigger for timestamp is enabled.
+ * @ts_all: Indicates if timestamp is enabled for all packets.
*/
struct cmb_dataset {
u32 trace_mode;
@@ -144,6 +155,9 @@ struct cmb_dataset {
u32 patt_mask[TPDM_CMB_MAX_PATT];
u32 trig_patt_val[TPDM_CMB_MAX_PATT];
u32 trig_patt_mask[TPDM_CMB_MAX_PATT];
+ bool patt_ts;
+ bool trig_ts;
+ bool ts_all;
};
/**
--
2.39.0
